Switching LDMOS device and method for making the same

ABSTRACT

A switching LDMOS device is formed first well in a semiconductor substrate that includes an LDD region and a first body doped region; a first heavily doped region serving as a source region is provided in the LDD region, and a second heavily doped region serving as a drain region is provided in the first body doped region; a channel of the switching LDMOS device is formed at a surface layer of the semiconductor substrate between the LDD region and the body doped region and below the gate structure; and one side of the LDD region and one side of the body doped region which are away from the gate structure both are provided with a field oxide or STI, and one side of the field oxide or STI is in contact with the first heavily doped region or the second heavily doped region.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority to Chinese Patent ApplicationNo. 202010321166.9 filed on Apr. 22, 2020, the entirety of which isincorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to the field of designing andmanufacturing semiconductor devices, in particular to a method formanufacturing a switching LDMOS device.

BACKGROUND OF THE INVENTION

Currently, the 5V switching LDMOS device employs the conventionalstructure of the CMOS. Referring to FIG. 1 , taking the most common Ntype LDMOS device structure as an example, FIG. 1 shows only some keystructures, and there are LDD regions in the P well. The source regionand drain region of the switching LDMOS device are respectively locatedin the LDD regions, there is a channel region between the two LDDregions, the substrate surface between the two LDD regions is providedwith a gate structure of the switching LDMOS device consisting of a gateoxide layer and a polysilicon gate, and gate sidewalls are furtherprovided at both sides of the gate structure along the channel lengthdirection.

The substrate surface is further provided with a field oxide (or STI).The field oxide isolates the heavily doped P type region from the LDDregion, and the heavily doped P type region serves as a leading-outregion to lead out the P well.

The general breakdown voltage BV of the 5V NMOS is 11.5 V, the channellength Lch is 0.6 um, and the square resistance Rsp is 2 MΩ/mm², whilethe general breakdown voltage BV of the 5V PMOS is 10.5 V, the channellength Lch is 0.5 um, and the square resistance Rsp is 7 MΩ/mm².

The current conventional manufacturing process of 5V MOS devices is asfollows:

First, an active region is planned on a semiconductor substrate such asa silicon substrate, then a well region is formed in the active region(regarding the PMOS, an N well is formed in the active region, andregarding the NMOS, a P well is formed in the active region), an oxidelayer is formed as a gate dielectric layer by means of the thermaloxidation method on the substrate surface, then a layer of polysiliconis deposited, a gate structure is formed by means of etching, an LDDregion is formed in the active region by means of ion implantation(regarding the PMOS, an N type LDD is formed, and regarding the NMOS, aP type LDD is formed), and then gate sidewalls are formed at both sidesof the gate structure by depositing oxide or nitride and by performingetching; and a heavily doped N type region and a heavily doped P typeregion are formed by means of self-aligned implantation. Regarding theNMOS, the heavily doped N type region serves as the source region anddrain region of the LDMOS device, and the heavily doped P type regionserves as the leading-out region of the well region.

The technical problems of the current CMOS process primarily lie in:

1. the BV cannot be high (≥15 V), being incapable of satisfying the newapplication scenarios;

2. the Rsp cannot continue to be reduced at high ratio, making itdifficult to reduce the chip area.

The reasons for the above problems are:

1. Since the formation process of the LDD region is a process ofimplantation through polysilicon, in order to prevent ion implantationfrom penetrating through the polysilicon, the ion implantation energy ofthe LDD cannot be very high, in which case the junction formed has arelatively small depth, which cannot satisfy the requirements of thehigh BV.

2. The formation process of the well region is shared by other basicdevices, and the surface concentration of the well region cannot reach arelatively high value, in which case a large channel length Lch isrequired to ensure the breakdown voltage BV, thereby limitingminiaturization of the device size.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present disclosure is toprovide a switching LDMOS device, to improve the problems that abreakdown voltage is difficult to increase and the device size isexcessively large.

Another technical problem to be solved by the present disclosure is toprovide a method for manufacturing the switching LDMOS device.

In order to solve the above-mentioned problems, the switching LDMOSdevice of the present disclosure is formed in a first well of a firstconductivity type in a semiconductor substrate, wherein the first wellcomprises an LDD region of the switching LDMOS device and a first bodydoped region of a second conductivity type; a gate structure of theswitching LDMOS device is formed on the surface of the substrate betweenthe LDD region and the body doped region of the second conductivitytype;

the gate structure comprises a gate dielectric layer covering thesubstrate surface and a polysilicon gate covering the gate dielectriclayer; gate sidewalls are further provided at both sides of the gatestructure;

a first heavily doped region of the second conductivity type is providedin the LDD region, one side of the first heavily doped region is incontact with the edge of the gate sidewall, and the first heavily dopedregion serves as a source region of the switching LDMOS device;

a second heavily doped region of the second conductivity type isprovided in the first body doped region, one side of the second heavilydoped region is in contact with the edge of the gate sidewall, and thesecond heavily doped region serves as a drain region of the switchingLDMOS device;

a channel of the switching LDMOS device is formed in a surface layer ofthe semiconductor substrate between the LDD region and the body dopedregion and below the gate structure, and when a voltage applied to thegate exceeds a threshold voltage of the LDMOS device, the channel isinverted to achieve conduction between the source region and the drainregion; and

one side of the LDD region and one side of the body doped region whichare away from the gate structure both are provided with a field oxide orSTI, and one side of the field oxide or STI is in contact with the firstheavily doped region in the LDD region or the second heavily dopedregion in the first body doped region.

In an embodiment, in the first well, a third heavily doped region of thefirst conductivity type is further provided at an outer side which awayfrom the gate structure of the field oxide or STI close to the firstbody doped region, and the third heavily doped region forms aleading-out region to lead the first well out of an electrode.

In an embodiment, a second gate structure is further provided on thefield oxide or STI, the second gate structure and the gate structure ofthe switching LDMOS device are synchronously formed by means of etching,the second gate structure is used as a mask for self-alignedimplantation of the first heavily doped region and the second heavilydoped region, or, the second gate structure is used as a mask forself-aligned implantation of the first heavily doped region or thesecond heavily doped region, and after the self-aligned implantation iscompleted, the second gate structure can be selectively removed orretained.

In an embodiment, the first body doped region of the second conductivitytype is formed by means of self-aligned implantation.

In an embodiment, the first conductivity type is a P type and the secondconductivity type is an N type; or the first conductivity type is an Ntype and the second conductivity type is a P type.

A switching LDMOS device is formed in a first well of a firstconductivity type in a semiconductor substrate, wherein:

the first well comprises a first body doped region of a secondconductivity type and a second body doped region of a first conductivitytype; a gate structure of the switching LDMOS device is formed on thesurface of the substrate between the first body doped region and thesecond body doped region;

the gate structure comprises a gate dielectric layer covering thesubstrate surface and a polysilicon gate covering the gate dielectriclayer; gate sidewalls are further provided at both sides of the gatestructure;

a first heavily doped region of the second conductivity type is providedin the second body doped region, one side of the first heavily dopedregion is in contact with the edge of the gate sidewall, and the firstheavily doped region serves as a source region of the switching LDMOSdevice;

a second heavily doped region of the second conductivity type isprovided in the first body doped region, one side of the second heavilydoped region is in contact with the edge of the gate sidewall, and thesecond heavily doped region serves as a drain region of the switchingLDMOS device;

a channel of the switching LDMOS device is formed in a surface layer ofthe semiconductor substrate between the second body doped region and thefirst body doped region and below the gate structure, and when a voltageapplied to the gate exceeds a threshold voltage of the LDMOS device, thechannel is inverted to achieve conduction between the source region andthe drain region; and

one side of the second body doped region and one side of the first bodydoped region which are away from the gate structure both are providedwith a field oxide or STI, and one side of the field oxide or STI is incontact with the first heavily doped region in the second body dopedregion or the second heavily doped region in the first body dopedregion.

In an embodiment, in the first well, a third heavily doped region of thefirst conductivity type is further provided at an outer side which awayfrom the gate structure of the field oxide or STI close to the firstbody doped region and the third heavily doped region forms a leading-outregion to lead the first well out of an electrode.

In an embodiment, a second gate structure is further provided on thefield oxide or STI, the second gate structure and the gate structure ofthe switching LDMOS device are synchronously formed by means of etching,the second gate structure is used as a mask for self-alignedimplantation of the first heavily doped region and the second heavilydoped region, or, the second gate structure is used as a mask forself-aligned implantation of the first heavily doped region or thesecond heavily doped region, and after the self-aligned implantation iscompleted, the second gate structure can be selectively removed orretained.

In an embodiment, the first body doped region and the second body dopedregion are formed by means of self-aligned implantation.

A method for manufacturing a switching LDMOS device comprises thefollowing process steps:

Step 1: providing a semiconductor substrate, wherein an active region isformed on the semiconductor substrate, the active region being used toform the switching LDMOS device; performing ion implantation in theactive region to produce a well region of the switching LDMOS device;and depositing an oxide layer on the surface of the semiconductorsubstrate, and then depositing a polysilicon layer on the oxide layer;

Step 2: etching the polysilicon layer and the oxide layer by means ofphotoresist definition, to form a gate structure of the switching LDMOSdevice, wherein the oxide layer serves as a gate dielectric layer, andthe polysilicon layer is etching-molded to form a polysilicon gate ofthe switching LDMOS device;

Step 3: applying a photoresist to define an implantation region of abody doped region by means of the photoresist, performing etching toopen an implantation window of the body doped region, and performing ionimplantation of the body doped region to form the body doped region ofthe switching LDMOS device;

Step 4: performing ion implantation in a well to form an LDD region ofthe switching LDMOS device;

Step 5: depositing an oxide layer or a nitride layer, and thenperforming etching to form gate sidewalls at both sides of the gatestructure of the switching LDMOS device; and

Step 6: performing ion implantation to form a heavily doped region, soas to produce a source region and a drain region of the switching LDMOSdevice.

In an embodiment, in Step 3, formation of the body doped region isformation of a first body doped region of a second conductivity type; ora first body doped region of the second conductivity type and a secondbody doped region of a first conductivity type both are formed in twosuccessive steps; the ion implantation of the first or second body dopedregion is self-aligned implantation under the definition of thephotoresist, and implantation energy can be adjusted according torequirements of a breakdown voltage, without a need to consider whethera hole is punched through the polysilicon layer, so as to achieve alarger implantation junction depth; and a process of forming a channelregion by means of the self-aligned implantation of the first or secondbody doped region is not shared by formation of other device structure,thereby increasing an implantation dose to increase an impurityconcentration of the surface of the channel region and reducing thedevice size.

In an embodiment, the first conductivity type is a P type and the secondconductivity type is an N type; or the first conductivity type is an Ntype and the second conductivity type is a P type.

In the switching LDMOS device of the present disclosure, the drainregion is or both the drain region and the source region are placed inthe body doped region, and the body doped region is defined by means ofthe photoresist and then is subject to targeted ion implantation. Theformation of the channel region using the self-aligned ion implantationwith the photoresist can be free of a limitation from other process oran effect of other structure, thereby achieving the objective ofincreasing the ion implantation energy and ion implantation dose, whichis difficult to be implemented in conventional processes. Higher ionimplantation energy can increase the junction depth, thereby making fulluse of the longitudinal depth of the LDD region, optimizing an electricfield distribution at a drain end, and increasing the breakdown voltageBV of the device. A higher ion implantation dose can increase thesurface concentration of the channel region, so the channel length Lchis reduced in the case where the breakdown voltage BV is ensured tosatisfy design requirements, thereby achieving the objective of reducingthe device size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural schematic diagram of an existing switching LDMOSdevice;

FIGS. 2-8 are diagrams of manufacturing process steps of a switchingLDMOS device according to Embodiment 1 of the present disclosure;

FIGS. 9-14 are diagrams of manufacturing process steps of a switchingLDMOS device according to Embodiment 2 of the present disclosure; and

FIG. 15 is a flow chart of a manufacturing process of a switching LDMOSdevice according to the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Regarding switching LDMOS devices, N LDMOS devices are primarily used inpractical applications, and therefore, an N LDMOS device is used as anexample for explanation in the embodiments of the present disclosure,that is, a first conductivity type is defined as a P type and a secondconductivity type is defined as an N type. A P LDMOS device can beproduced by inverting the related conductivity types.

Referring to FIG. 8 , which is a switching LDMOS device of the presentdisclosure, in Embodiment 1 of the switching LDMOS device provided bythe present disclosure: the LDMOS device is formed in a first well of aP type in a semiconductor substrate, that is, a P well 1. The P well 1includes an LDD region 4 of the switching LDMOS device and a first bodydoped region 2 of a N type. A gate structure of the switching LDMOSdevice is formed on the surface of the substrate between the LDD regionand the body doped region 2 of the N type.

The gate structure includes a gate dielectric layer covering thesubstrate surface and a polysilicon gate 3 covering the gate dielectriclayer. Gate sidewalls 8 are further provided at both sides of the gatestructure.

An N type first heavily doped region 5 a is provided in the LDD region4, one side of the first heavily doped region 5 a is in contact with theedge of the gate sidewall 8, and the N type first heavily doped region 5a serves as a source region of the switching LDMOS device.

An N type second heavily doped region 5 b is provided in the first bodydoped region 2, one side of the second heavily doped region 5 b is incontact with the edge of the gate sidewall 8, and the second heavilydoped region 5 b serves as a drain region of the switching LDMOS device.

A channel of the switching LDMOS device is formed in a surface layer ofthe semiconductor substrate between the LDD region and the body dopedregion and below the gate structure, the length of the channel is Lch,and when a voltage applied to the gate exceeds a threshold voltage ofthe LDMOS device, the channel is inverted to achieve conduction betweenthe source region 5 a and the drain region 5 b.

One side of the LDD region 4 and one side of the body doped region 2which are away from the gate structure both are provided with a fieldoxide 7 (or STI), and one side of the field oxide 7 is in contact withthe first heavily doped region 5 a in the LDD region 4 or the secondheavily doped region 5 b in the first body doped region 2.

In the first well 1, a P type third heavily doped region 6 is furtherprovided at an outer side of the field oxide or STI of the first bodydoped region and away from the gate structure, and the third heavilydoped region 6 forms a leading-out region to lead the first well 1 outof an electrode.

Still referring to FIG. 8 , a second gate structure is further providedon the field oxide 7, for example, the field oxide between the secondheavily doped region 5 b and the third heavily doped region 6. Thesecond gate structure and the gate structure of the switching LDMOSdevice are synchronously formed by means of etching, and the second gatestructure is used as a mask for self-aligned implantation of the firstheavily doped region and the second heavily doped region and has noelectrical property, or, the second gate structure is used as a mask forself-aligned implantation of the first heavily doped region or thesecond heavily doped region and has no electrical property. After theself-aligned implantation is completed, the second gate structure can beselectively removed or retained.

Referring to Embodiment 2 shown by FIG. 14 , which is another switchingLDMOS device of the present disclosure, the switching LDMOS device isformed in a P type first well 1 in a semiconductor substrate.

The first well 1 includes an N type first body doped region 2 and a Ptype second body doped region 9. A gate structure of the switching LDMOSdevice is formed on the surface of the substrate between the first bodydoped region 2 and the second body doped region 9.

The gate structure includes a gate dielectric layer covering thesubstrate surface and a polysilicon gate 3 covering the gate dielectriclayer. Gate sidewalls 8 are further provided at both sides of the gatestructure.

An N type first heavily doped region 5 a is provided in the second bodydoped region 9, one side of the first heavily doped region 5 a is incontact with the edge of the gate sidewall 8, and the first heavilydoped region 5 a serves as a source region of the switching LDMOSdevice.

An N type second heavily doped region 5 b is provided in the first bodydoped region 1, one side of the second heavily doped region 5 b is incontact with the edge of the gate sidewall 8, and the second heavilydoped region 5 b serves as a drain region of the switching LDMOS device.

A channel of the switching LDMOS device is formed in a surface layer ofthe semiconductor substrate between the second body doped region 9 andthe first body doped region 1 and below the gate structure, and when avoltage applied to the gate exceeds a threshold voltage of the LDMOSdevice, the channel is inverted to achieve conduction between the sourceregion and the drain region.

One side of the second body doped region 9 and one side of the firstbody doped region 2 which are away from the gate structure both areprovided with a field oxide 7, and one side of the field oxide 7 is incontact with the first heavily doped region in the second body dopedregion or the second heavily doped region in the first body dopedregion.

In the first well 1, a P type third heavily doped region 6 is furtherprovided at an outer side of the field oxide 7 which away from the gatestructure of the first body doped region 2, and the third heavily dopedregion 6 forms a leading-out region to lead the first well 1 out of anelectrode.

Similar to Embodiment 1, a second gate structure is further provided onthe field oxide. The second gate structure and the gate structure of theswitching LDMOS device are synchronously formed by means of etching, andthe second gate structure is used as a mask for self-alignedimplantation of the first heavily doped region and the second heavilydoped region, or, the second gate structure is used as a mask forself-aligned implantation of the first heavily doped region or thesecond heavily doped region. After the self-aligned implantation iscompleted, the second gate structure can be selectively removed orretained.

In Embodiment 2, the P type body region 9 is also formed by means of ionimplantation at the source end. Therefore, the entire device is providedwith a body region at the peripheries of the source region and the drainregion, respectively. In the two embodiments described above, the firstbody doped region 2 and the second body doped region 9 are both formedby means of self-aligned implantation.

Referring to FIGS. 2-8 , regarding the structure of Embodiment 1, amethod for manufacturing a switching LDMOS device of the presentdisclosure includes the following process steps:

Step 1: Referring to FIG. 2 , a semiconductor substrate 1 is provided,wherein an active region is formed on the semiconductor substrate, theactive region being used to form the switching LDMOS device; ionimplantation is performed in the active region to produce a well regionof the switching LDMOS device; form field oxide 7, and an oxide layer isdeposited on the surface of the semiconductor substrate, and then apolysilicon layer 3 is deposited on the oxide layer.

Step 2: Referring to FIG. 3 , the polysilicon layer 3 and the oxidelayer are etched by means of photoresist definition, to form a gatestructure of the switching LDMOS device, wherein the oxide layer servesas a gate dielectric layer, and the polysilicon layer 3 isetching-molded to preliminarily form a polysilicon gate of the switchingLDMOS device.

Step 3: A photoresist is applied to define an implantation region of abody doped region by means of the photoresist, etching is performed toopen an implantation window of the body doped region, and ionimplantation of the body doped region is performed to form the bodydoped region of the switching LDMOS device. In actual processapplications or design scenarios, the structure of Embodiment 1 and thestructure of Embodiment 2 may exist separately or coexist. In Embodiment1, the two structures coexist. During P well implantation of thestructure of Embodiment 2, since the structure of Embodiment 1 is notsubject to P well implantation, P type implantation occurs for the firsttime in the structure of Embodiment 1 as shown in FIGS. 4 and 5 , but nowindow is opened by means of the photoresist. Referring to FIGS. 6 and 7, during implantation of the N type body region, the implantation windowof the N type body region is opened by means of the photoresist, and theion implantation is performed to form the N type body region 2.

Step 4: Ion implantation is performed in a well 1 to form an LDD region4 of the switching LDMOS device. This is an optional step, and adetermination as to whether LDD implantation is to be performed can beperformed as needed.

Step 5: An oxide layer or a nitride layer is deposited, and then etchingis performed to form gate sidewalls 8 at both sides of the gatestructure of the switching LDMOS device.

Step 6: Ion implantation is performed to form a heavily doped region, soas to produce a source region 5 a and a drain region 5 b of theswitching LDMOS device, thereby completing production of the device,finally forming the device as shown in FIG. 8 .

Referring to FIGS. 2, 9-14 , regarding the structure of Embodiment 2, amethod for manufacturing a switching LDMOS device of the presentdisclosure includes the following process steps:

Step 1: Referring to FIG. 2 , a semiconductor substrate is provided,wherein an active region is formed on the semiconductor substrate, theactive region being used to form the switching LDMOS device; ionimplantation is performed in the active region to produce a well regionof the switching LDMOS device; a field oxide is formed; and an oxidelayer is deposited on the surface of the semiconductor substrate, andthen a polysilicon layer is deposited on the oxide layer.

Step 2: Referring to FIG. 9 , the polysilicon layer 3 and the oxidelayer are etched by means of photoresist definition, to form a gatestructure of the switching LDMOS device, wherein the oxide layer servesas a gate dielectric layer, and the polysilicon layer is etching-moldedto preliminarily form a polysilicon gate of the switching LDMOS device.

Step 3: A photoresist is applied to define an implantation region of abody doped region by means of the photoresist, etching is performed toopen an implantation window of the body doped region, and ionimplantation of the body doped region is performed to form the bodydoped region of the switching LDMOS device. Referring to FIGS. 10-13 ,in this embodiment, ion implantation of the P type body region 9 and theN type body region 2 is performed. First, the photoresist is used fordefinition, and the ion implantation window of the P type body region isopened by means of the photoresist. Referring to FIG. 10 , an ionimplantation process of the P type body region 9 is performed; then anion implantation window of the N type body region 2 is defined by meansof the photoresist 10, referring to FIG. 12 , an ion implantationprocess of the N type body region is performed, to form the N type bodyregion 2.

The ion implantation processes of the P-type body region and the N typebody region described in the present disclosure both are performed underthe cover of the photoresist. Therefore, the ion implantation energy canbe increased as needed to increase an implantation junction depth,without a need to consider the case where excessively high ionimplantation energy punches a hole through the polysilicon layer; and anion concentration on the surface of a channel region can be increased byadjusting an ion implantation dose, thereby reducing a square resistanceRsp, reducing the device size by reducing the channel length Lch in thecase where a desired breakdown voltage performance is achieved,improving the integration level, and reducing the cost.

Step 4: Ion implantation is performed in a well 1 to form an LDD region4 of the switching LDMOS device. This is an optional step, and adetermination as to whether LDD implantation is to be performed can beperformed as needed.

Step 5: An oxide layer or a nitride layer is deposited, and then etchingis performed to form gate sidewalls 8 at both sides of the gatestructure of the switching LDMOS device.

Step 6: Ion implantation is performed to form a heavily doped region, soas to produce a source region 5 a and a drain region 5 b of theswitching LDMOS device, thereby completing production of the device,finally forming the device as shown in FIG. 14 .

The above embodiments are merely some embodiments of the presentdisclosure and are not intended to limit the present disclosure. Forthose skilled in the art, the present disclosure may have variousmodifications and changes. Any modification, equivalent replacement,improvement, etc. performed within the spirit and principle of thepresent disclosure shall fall within the protection scope of the presentdisclosure.

EXPLANATIONS FOR REFERENCE NUMERALS OF THE DRAWINGS

-   -   1. first well;    -   2. first body doped region (Nbody);    -   3. polysilicon gate;    -   4. LDD region;    -   5 a. first heavily doped region;    -   5 b. second heavily doped region;    -   6. third heavily doped region;    -   7. field oxide;    -   8. gate sidewall;    -   9. second body doped region (Pbody); and    -   10. photoresist.

What is claimed is:
 1. A switching LDMOS device comprising: a firstconductivity type formed in a first well in a semiconductor substrate,wherein the first well comprises an LDD region and a body doped regionof a second conductivity type, wherein the LDD region and the body dopedregion are laterally-spaced with the semiconductor substrate disposedtherebetween, and a depth of the body doped region in the semiconductorsubstrate is greater than a depth of the LDD region in the semiconductorsubstrate; a gate structure formed on a surface of the substratedisposed between the LDD region and the body doped region of the secondconductivity type, wherein the gate structure comprises a gatedielectric layer having a substantially uniform thickness covering thesubstrate surface, a polysilicon gate covering the gate dielectriclayer, and gate sidewalls formed at opposing sides of the gatestructure; a first heavily doped region of the second conductivity typeprovided in the LDD region, wherein one side of the first heavily dopedregion is in contact with an edge of one of the gate sidewalls, and thefirst heavily doped region serves as a source region; a second heavilydoped region of the second conductivity type provided in the body dopedregion, wherein one side of the second heavily doped region is incontact with an edge of the other one of the gate sidewalls, and thesecond heavily doped region serves as a drain region; a channel formedin a surface layer of the semiconductor substrate disposed between theLDD region and the body doped region and below the gate structure, andwherein when a voltage applied to the gate exceeds a threshold voltageof the switching LDMOS device, the channel is inverted to achieveconduction between the source region and the drain region; and a fieldoxide or STI provided at one side of the LDD region and at one side ofthe body doped region which are away from the gate structure, andwherein one side of the field oxide or STI is in contact with the firstheavily doped region in the LDD region or the second heavily dopedregion in the first body doped region.
 2. The switching LDMOS deviceaccording to claim 1, further comprising: a third heavily doped regionof the first conductivity type formed in the first well provided at anouter side of the field oxide or STI adjacent to the first body dopedregion, wherein the third heavily doped region forms a leading-outregion to lead the first well out of an electrode.
 3. The switchingLDMOS device according to claim 1, further comprising: a second gatestructure provided on the field oxide or STI adjacent to the first bodydoped region, wherein the second gate structure and the gate structureare synchronously formed by means of etching, the second gate structureis used as a mask for self-aligned implantation of the first heavilydoped region and/or the second heavily doped region, and after theself-aligned implantation is completed, the second gate structure can beselectively removed or retained.
 4. The switching LDMOS device accordingto claim 1, wherein the first body doped region of the secondconductivity type is formed by means of self-aligned implantation. 5.The switching LDMOS device according to claim 1, wherein the firstconductivity type is a P type and the second conductivity type is an Ntype; or the first conductivity type is an N type and the secondconductivity type is a P type.
 6. A switching LDMOS device comprising: afirst conductivity type formed in a first well in a semiconductorsubstrate, wherein the first well comprises a first body doped region ofa second conductivity type and a second body doped region of a firstconductivity type, wherein the first body doped region and the secondbody doped region are laterally-spaced with the semiconductor substratedisposed therebetween, a depth of the first body doped region in thesemiconductor substrate is substantially the same as a depth of thesecond body doped region in the semiconductor substrate and the depthsof the first body doped region and the second body doped region extendsubstantially into the substrate; a gate structure formed on a surfaceof the substrate disposed between the first body doped region and thesecond body doped region, wherein the gate structure comprises a gatedielectric layer having a substantially uniform thickness covering thesubstrate surface, a polysilicon gate covering the gate dielectriclayer, and gate sidewalls formed at opposing sides of the gatestructure; a first heavily doped region of the second conductivity typeprovided in the second body doped region, wherein one side of the firstheavily doped region is in contact with an edge of one of the gatesidewalls, and the first heavily doped region serves as a source region;a second heavily doped region of the second conductivity type providedin the first body doped region, wherein one side of the second heavilydoped region is in contact with an edge of the other one of the gatesidewalls, and the second heavily doped region serves as a drain region;a channel formed in a surface layer of the semiconductor substratedisposed between the second body doped region and the first body dopedregion and below the gate structure, and wherein when a voltage appliedto the gate exceeds a threshold voltage of the switching LDMOS device,the channel is inverted to achieve conduction between the source regionand the drain region; and a field oxide or STI provided at one side ofthe second body doped region and at one side of the first body dopedregion which are away from the gate structure, and wherein one side ofthe field oxide or STI is in contact with the first heavily doped regionin the second body doped region or the second heavily doped region inthe first body doped region.
 7. The switching LDMOS device according toclaim 6, further comprising: a third heavily doped region of the firstconductivity type formed in the first well provided at an outer side ofthe field oxide or STI adjacent to the first body doped region, whereinthe third heavily doped region forms a leading-out region to lead thefirst well out of an electrode.
 8. The switching LDMOS device accordingto claim 6, further comprising: a second gate structure provided on thefield oxide or STI adjacent to the first body doped region, wherein thesecond gate structure and the gate structure are synchronously formed bymeans of etching, the second gate structure is used as a mask forself-aligned implantation of the first heavily doped region and thesecond heavily doped region, or, the second gate structure is used as amask for self-aligned implantation of the first heavily doped region orthe second heavily doped region, and after the self-aligned implantationis completed, the second gate structure can be selectively removed orretained.
 9. The switching LDMOS device according to claim 6, whereinthe first body doped region and the second body doped region are formedby means of self-aligned implantation.